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Summary: We are seeking a Lead Digital Verification Engineer to join NXP’s NVM IP design group in Bangalore, India. This role involves leading and managing verification activities for a diverse NVM IP portfolio of L-NVM, RRAM and MRAM, developing and maintaining verification flow and environment, and collaborating with NXP product design teams to deliver high-quality, scalable NVM IP solutions across multiple business verticals. Job Responsibility: · Responsible for the pre-silicon verification of non-volatile memory controller modules. · Responsible for defining digital verification strategy and plan for IP modules. · Interface to Digital design teams to understand functionality and application of the IP subsystem, SoC system. · Responsible for executing verification plan according to the product specification and verification requirements defined. · Responsible for developing, debugging and running System Verilog UVM based verification environment for RTL/netlist simulation. · Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level), run regression, collect and analyze code/functional coverage. Job Qualification: · Bachelor’s degree or above in Microelectronics, Electronics, Electri
Dutch company
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