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We are seeking a talented Physical Verification Design Engineer to join our VLSI design team. This role involves ownership of full-chip and block-level physical verification (PV) signoff, ensuring designs meet foundry and reliability requirements. The candidate will collaborate closely with physical design, PDK, CAD, and tapeout teams to deliver high-quality silicon. Key Responsibilities • Perform physical verification (PV) for block-level and full-chip designs, including: • Design Rule Check ( DRC ) • Layout Versus Schematic ( LVS ) • Electrical Rule Check ( ERC ) • Antenna, density, and reliability checks • Drive signoff closure by identifying and resolving PV violations efficiently. • Work with physical design and layout teams to debug and fix violations. • Develop and maintain runsets, decks, and automation flows using industry-standard tools. • Analyze foundry decks and PDK updates , ensuring compliance with process requirements. • Lead tapeout readiness reviews and ensure high-quality database delivery. • Perform hierarchical verification and regression management . • Participate in improving verification methodologies, runtime, and capacity optimization . • Interface with foundry and EDA vendors to resolve tool or deck-related issues. • Mentor junior engineers and review their work as needed. Preferred / Added Advantage Skills • Exposure to Physical Design (PD) con
Dutch company
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